The density of dynamic random access memory (DRAM) devices has increased dramatically in recent years. Today 64 megabit (MB) devices, each on a single chip with an area of several tens of square millimeters, are commonplace and 256 MB devices with areas under a hundred square millimeters are becoming available. Operating speeds have increased from 50 MHz to over 500 MHz.
In earlier DRAM systems data transfer to or from a memory controller was asynchronous to the system clock to which the controller operations are referenced. But a problem arises with higher speed systems in that all timing parameters for the DRAM must be met for a particular speed sort. In other words, missing or failing to meet any timing parameter can down-sort a very fast part of the system into a slower access bin. This problem gave rise to the development of a synchronous DRAM (SDRAM) which is designed to have an input address and command interface more similar to that of the memory controller. The SDRAMs are that class of memory units which use the system clock to synchronize the interface between the memory controller and the DRAM arrays. Based on operating frequency and number of bits transferred per clock cycle, SDRAMs can provide substantial bandwidth increase over previous DRAMs.
The rapid increase in process and functional complexity in today's synchronous dynamic random access memory (SDRAM) products and VLSLs in general, creates a need for high resolution test methodologies. This requirement is driven by the need to reveal and to characterize subtle process and design interactions that may occur in the product during the technology and design development phase of the product effort. Also, once the product is qualified and in manufacturing production, precision test methodologies are required for code signal development, process learning, and also for yield and product improvement. The invention described hereinafter will illustrate the techniques utilized to implement a "Test Mode" architecture on a 256 MB SDRAM, by way of example. The invention however is applicable to VLSI products in general, as well as other products, and is not restricted solely to SDRAMs.
It is industry practice to subject products, such as SDRAMs, to a period of testing and "burn-in" before they are shipped from the factory. During burn-in the products are operated at substantially higher than normal voltages and temperatures in order to artificially stress them and thereby weed out of a given population of devices those which possibly would fail prematurely in actual operation. A burn-in period may, for example in the case of 256 MB SDRAMs, take as long as sixteen hours. Various test signals applied to the individual devices during a burn-in period are used in an attempt to find inadequate or improper operation of a given device, such as caused by microscopic defects or variations in the physical and/or electrical conditions within that device. It is desirable to be able to shorten by a substantial amount the time required for burn-in, and also to have more effective test signals and a better way of applying them to each device (e.g., an SDRAM) in order to reveal undesirable performance interactions or deficiencies within the device among its various memory arrays or sections. The present invention provides improved test methodologies for VLSIs in general, and SDRAMs in particular, as well as improved products resulting therefrom.